1. Field of the Invention
The invention is related to a system on chip (SOC) that includes a network on chip (NOC), and in particular, to a SOC that includes a network on chip (NOC) and further includes an integrated test processor (ITP).
2. Description of the Prior Art
Computers and computerized devices have become increasingly more complex. As a result of modern fabrication technology, integrated circuits (i.e., chips) have become smaller and smaller. This has been achieved while including larger number of components and while achieving more and more functions.
This increased complexity has lead to increased cost and difficulty in manufacturing. The increasing number of components and circuits require more and more testing to ensure functionality and reliability. Many computers and computerized devices employ specialized on-chip circuitry in order to perform testing on the chip before it can be approved and sold to customers.
One area of electronics in which chip complexity has dramatically increased is in the area of communication chips. The increased reliance on communication networks, such as packet-based networks and public switched telephone networks (PSTNs), for example, has lead to the development of more powerful communications circuits and functions on chips. Such communications continue to demonstrate a need for increased methods and devices for testing the chips. Rigorous and complete testing is needed in order to test a chip design for proper and efficient operation before manufacture, in order to test chips during manufacture to ensure that quality meets acceptable levels, and in order to test the chips during operation in order to ensure continued proper operation.